XC5210-PQ160:Field Programmable Gate Arrays

XC5210-PQ160
1.109pcs in stock
2.QFP,new and original factory sealed!

 XC5210-PQ160:Field Programmable Gate Arrays

 

Description
The XC5200 Field-Programmable Gate Array Family is engineered to deliver low cost. Building on experiences gained with three previous successful SRAM FPGA fami-
lies, the XC5200 family brings a robust feature set to programmable logic design. The VersaBlock™ logic module, the VersaRing I/O interface, and a rich hierarchy of inter-
connect resources combine to enhance design flexibility and reduce time-to-market. Complete support for the XC5200 family is delivered through the familiar Xilinx soft-
ware environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, sche-
matic capture, VHDL, and Verilog HDL synthesis. Designers utilizing logic synthesis can use their existing tools to design with the XC5200 devices.

 

Features
• Low-cost, register/latch rich, SRAM based
reprogrammable architecture
-0.5µm three-layer metal CMOS process technology
- 256 to 1936 logic cells (3,000 to 23,000 “gates”)
- Price competitive with Gate Arrays
• System Level Features
- System performance beyond 50 MHz
- 6 levels of interconnect hierarchy
- VersaRing™ I/O Interface for pin-locking
- Dedicated carry logic for high-speed arithmetic
functions
- Cascade chain for wide input functions
- Built-in IEEE 1149.1 JTAG boundary scan test
circuitry on all I/O pins
- Internal 3-state bussing capability
- Four dedicated low-skew clock or signal distribution
nets
• Versatile I/O and Packaging
- Innovative VersaRing™ I/O interface provides a high
logic cell to I/O ratio, with up to 244 I/O signals
- Programmable output slew-rate control maximizes
performance and reduces noise
- Zero Flip-Flop hold time for input registers simplifies
system timing
- Independent Output Enables for external bussing